1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device for 4F2 having a vertical channel transistor.
2. Description of the Related Art
As the integration rate of semiconductor memory devices increases, the area of unit cells decreases. The minimum feature size of cells is reduced to correspond to a decrease in the area of unit cells. However, if the minimum feature size is reduced, the length and width of a channel of a device decrease, resulting in degrading a current driving ability of the device and degrading the characteristics of the device due to a short channel effect.
Thus, various approached for reducing the area of unit cells without reducing the minimum feature size have been studied. As one of the approaches, a vertical channel transistor in which source and drain regions are disposed vertically within an active region to have a vertical channel such that even when the area of unit cells decreases, the length of the channel is not decreased, has been suggested. The vertical channel transistor has advantages of a high current driving ability and a small leakage current caused by drain induced barrier lowering (DIBL) or punch through.
In implementing the vertical channel semiconductor device, in general, a buried bit line structure in which bit lines are buried in a device isolation region of a cell, and a structure in which gate lines are formed on a circumference of a pillar where a vertical channel is formed, are used. However, these structures are formed within a semiconductor substrate and thus are more complex than a general structure in which bit lines and gate lines are sequentially stacked on a semiconductor substrate and processes are very complicated.